1. Field of the Invention
The present invention relates to a method for controlling power for a semiconductor storage device having a memory cell which must be refreshed to maintain data and the semiconductor storage device employing the method for controlling power.
The present application claims priority of Japanese Patent Application No. 2001-256913 filed on Aug. 27, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 13 is a block diagram showing an example of configurations of a conventional semiconductor storage device having a memory cell which must be refreshed to maintain data. The conventional semiconductor storage device is a DRAM (Dynamic Random Access Memory) having a storage capacity of 64 Mbits and is made up of four banks and having a number of refresh processes denoting a number of rows in each of memory cell arrays 111 to 114 activated by one time refresh process being 4096 (=212). The conventional semiconductor storage device chiefly includes four pieces of banks 11 to 14, column decoder groups 21 to 24, row decoder groups 31 to 34, an input buffer 4, an output buffer 5, a multiplexer (MUX) 6, a command decoder 7, a row column address buffer 8, a refresh counter 9, and a self-refresh circuit 10.
Each of the banks 11 to 14 includes each of the memory cell arrays 111 to 114 and each of sense amplifiers/input and output buses (SA-IOB) 121 to 124. Each of the memory cell arrays 111 to 114 has a storage capacity of 16 Mbits in which a plurality of pieces of memory cells is arranged in a matrix form. Each of sense amplifiers (SAs) making up each of the SA-IOB 121 to 124 detects data read from a memory cell on a column of corresponding memory cell arrays 111 to 114 being selected by a row decoder making up the corresponding row decoder groups 31 to 34 to a bit line and amplifies the detected data. Each of the input/output buses (IOBs) making up each of the SA-IOBs 121 to 124, while being connected to a global input/output bus 13, at a time of reading data, transmits data detected and amplified by each of the corresponding SAs to the global input/output bus 13 while, at a time of writing data, transmits the data transmitted by the global input/output bus 13 to a memory cell selected out of the corresponding memory cell arrays 111 to 114.
Each of the column decoder groups 21 to 24 is mounted on each of the banks 11 to 14 and has a plurality of column decoders. Each of the column decoders operates to decode a column address fed from a row column address buffer 8 and outputs a plurality of column selection switching signals used to put each of the SAs being connected to corresponding bit lines of each of memory cell arrays 111 to 114 into a selection state. Each of the row decoder groups 31 to 34 is mounted on each of the banks 11 to 14 and has a plurality of row decoders. Each of the row decoders decodes a row address fed from the row column address buffer 8 and puts a corresponding word line of each of the memory cell arrays 111 to 114 into the selection state.
The input buffer 4 being connected commonly to the banks 11 to 14 amplifies and buffers data being input a data input/output terminal DQ and then feeds it to the MUX 6. The output buffer 5 being connected commonly to the banks 11 to 14 amplifies and buffers data fed from the MUX 6 and outputs sequentially it from the data input/output terminal DQ. The MUX 6 feeds data supplied through the global input and output bus 13 from the IOBs making up the SA-IOB 121 to 124 to the output buffer 5 and data fed from the input buffer 4 through the global input/output bus 13 to the IOBs making up SA-IOB 121 to 124.
The command decoder 7, when a clock enable signal CKE fed from an external is changed from its high to low level, decodes a chip select signal/Cs, row address strobe signal/RAS, column address strobe signal/CAS, and write enable signal/WE fed in synchronization with a clock CLK fed from an external and, if it is judged that operations are in a self-refresh mode (entry), produces a high-level self-refresh start signal SRT and feeds the row column address buffer 8 and the self-refresh circuit 10. The self-refresh start signal SRT is used to instruct a self-refresh process to be started. Also, the command decoder 7 produces a row activated signal xcfx86 RAS based on a self-refresh signal xcfx86 SRF supplied from the self-refresh circuit 10 and feeds it to a row column address buffer 8. The self-refresh signal xcfx86 SRF is an original signal from which the row activated signal xcfx86 RAS is produced and is used to set a basic period for the self-refresh process. The row activated signal xcfx86 RAS is a basic signal used to activate row-based components such as the row decoder groups 31 to 34 or a like. Moreover, the clock enable signal CKE is active high while the chip select signal/CS, row address strobe signal/RAS, column address strobe signal/CAS, and write enable signal/WE are all active low.
The row column address buffer 8, while an ordinary operation is being performed, produces a column address and a row address based on an address AD fed from an external and the row address is fed to a plurality of row decoders making up each of the row decoder groups 31 to 34 with timing when a row activated signal xcfx86 RAS is fed from a command decoder 7. Also, the row column address buffer 8, when a self-refresh start signal SRT is fed from the command decoder 7 at a time of the self-refresh process, based on a counter value RCT supplied from the refresh counter 9, produces a row address for the self-refresh process and, with timing when a row activated signal xcfx86 RAS supplied from the command decoder 7 is fed, feeds the row address to the plurality of row decoders making up each of the row decoder groups 31 to 34. In the refresh counter 9, at the time of a self-refresh process, its counter value RCT is updated and the updated counter value RCT is fed to the row column address buffer 8. The self-refresh circuit 10, based on a high-level self-refresh start signal SRT supplied from the command decoder 7, produces a self-refresh signal xcfx86 SRF in a period of a clock produced by an oscillator (not shown) mounted therein and feeds it to the command decoder 7.
Next, internal operations of the semiconductor storage device having configurations described above to be performed at a time of the self-refresh process will be described by referring to a timing chart shown in FIG. 14. First, the clock enable signal CKE, as shown in FIG. 14 (2), remains high in an initial state before time t1 and the clock CLK changes to be low in synchronization with a rise of a clock CLK at the time t2 (see FIG. 14(1)). That is, in the initial state before the time t1, an internal state ST of the conventional semiconductor storage device is an idle state IST in which no operation is performed, as shown in FIG. 14(4).
In such the initial state, the clock enable signal CKE (see FIG. 14(1)) changes to be low in synchronization with a rise of a clock CLK at the time t2 as shown in FIG. 14(2) and, as shown in FIG. 14(3), a command SRC, one of a command CMD, used to instruct setting of a self-refresh mode is fed. The command SRC is fed when, for example, a low-level chip selector signal/CS, low-level row address strobe signal/RAS, low-level column address strobe signal/CAS and high-level write enable signal/WE are supplied in synchronization with the clock CLK. This makes the command decoder 7 decode the low-level chip select signal/CS, low-level row address strobe signal/RAS, low level column address strobe signal/CAS and high-level write enable signal/WE and judges that operations are set to be in a self-refresh mode. Therefore, the command decoder 7 produces a high-level self-refresh start signal SRT shown in FIG. 14(5) and feeds it to the self-refresh circuit 10.
This causes the internal state ST of the conventional semiconductor storage device to be changed from its idle state IST to its self-refresh state SRST, as shown in FIG. 14(4). That is, the self-refresh circuit 10, based on a high-level self-refresh start signal SRT fed from the command decoder 7, in a period of a clock produced by the oscillator mounted therein, produces a self-refresh signal xcfx86 SRF shown in FIG. 14(6) and feeds it to the command decoder 7. This causes the command decoder 7 to produce, based on a self-refresh signal xcfx86 SRF fed from the self-refresh circuit 10, a row activated signal xcfx86 RAS shown in FIG. 14(7) and feeds it to the row column address buffer 8. Therefore, the row column address buffer 8, when a self-refresh start signal SRT is fed from the command decoder 7, based on a counter value RCT supplied from the refresh counter 9, produces a row address to be used for the self-refresh process and feeds it to each of a plurality of row decoders making up each of the row decoder groups 31 to 34 with timing when a row activated signal xcfx86 RAS is fed from the command decoder 7. Thereafter, in the conventional semiconductor storage device, a refresh process is performed at equal intervals on all word lines (4096 cycles) in a period of a clock (hereinafter referred to be a refresh period TR) produced by an oscillator mounted within the self-refresh circuit 10. Since the conventional semiconductor storage device is a DRAM (Dynamic Random Access Memory) having a number of refresh processes denoting a number of rows of a memory cell array activated by one time refresh process being 4096 (=212), so long as the refresh process is not performed, if time during which data is not lost (being referred to as a real refreshing capability tREF) is 64 msec, the refresh period TR is set, in advance, to be 15.6 xcexcsec (FIG. 14(6)). On the other hand, if the real refreshing capability tREF is 128 msec, the refresh period TR is set to be 31.2 xcexcsec.
Next, to exit the self-refresh mode, for example, at the time t3, as shown in FIG. 14(2), regardless of a rising edge of the clock CLK (see FIG. 14(1)) at the time t3, a clock enable signal CKE is changed from its low to high level. This causes the command decoder 7 to change a self-refresh start signal SRT from its high to low level and feeds it to the self-refresh circuit 10. Therefore, the self-refresh circuit 10, based on a low-level self-refresh start signal SRT fed from the command decoder 7, as shown in FIG. 14(6), stops production of a self-refresh signal xcfx86 SRF. As a result, the command decoder 7, since a self-refresh signal xcfx86 SRF is not fed from the self-refresh circuit 10, as shown in FIG. 14(7), stops the production of a row activated signal xcfx86 RAS. By operations described above, the internal state ST of the conventional semiconductor storage device, as shown in FIG. 14(4), changes from its self-refresh state SRST to its idle state IST. Moreover, when the clock enable signal CKE is changed from its low to high level, if a refresh process is performed, after the refresh process has finished, the internal state ST of the conventional storage device changes from its self-refresh state SRST to its idle state IST.
In a self-refresh mode, in a standby state where a system such as a computer or a like, in which DRAMs are mounted, is not accessed from an external, data being stored in a memory cell is periodically and automatically held. Therefore, in the self-refresh mode, refresh processes are not directly related to operations of systems, it is thus desirous that power consumption is made as small as possible. In recent years in particular, portable electronic devices are widely used and, in the semiconductor storage device being mounted in portable electronic devices, more reduction in power consumption is required and a specification of current consumption becomes more rigorous (conventionally being specified to be about 1 mA. However, it is now about 100 xcexcA ). Here, the portable electronic device includes notebook-type, palm-type, and pocket-type computers, or a like, a PDA (Personal Digital Assistance), portable cellular phone, PHS (Personal Handy-phone System), or a like.
Next, a reason why power consumption in the portable electronic device has to be reduced will be described. In portable electronic devices, power is supplied from a battery, a dry cell, or a like and a power source voltage of the portable electronic device is lower than that of a stationary type electronic device whose power is supplied from a commercial power source. Therefore, a power source voltage employed in the semiconductor storage device being mounted in portable electronic devices is made lower which, as a result, causes a threshold voltage of a transistor making up peripheral devices such as an input buffer 4 or output buffer 5 to be made lower. A leak current (sub-threshold leak current) occurring in a standby state in such the peripheral circuits tends to increase due to such lowering in the threshold voltage of the transistor making up the peripheral circuits.
Moreover, as described above, in the semiconductor storage device being mounted on portable electronic devices, due to rigorous specifications of current consumption, a current being consumed at a time of refreshing is reduced and, as a result, not only a minute leak current but also the sub-threshold leak current occurring due to defective processes in each of the memory cells may not be negligible. However, in the conventional semiconductor storage device, in its self-refresh mode, as described above, only a thing that is done therein is to perform a periodical refresh process at a refresh period TR having been set in advance according to the real refreshing capability tREF in the semiconductor storage device. Therefore, in the above conventional semiconductor device, a data maintaining current is determined by the real refreshing capability tREF and an alternating current cannot be reduced and rigorous specifications of current consumption are not met. Moreover, a direct current such as a leak current, minute leak current, or a like that tend to increase cannot be reduced.
In view of the above, it is an object of the present invention to provide a method for controlling power for a semiconductor storage device and the semiconductor storage device which enable power consumption to be greatly reduced in a standby state.
According to a first aspect of the present invention, there is provided a method for controlling power for a semiconductor storage device having a memory cell which must be refreshed to maintain data, including:
a step of employing an ultra-low power consumption mode in which power control is exerted in a standby state and in which a centralized refresh state, power-OFF state, and power-ON state are provided, and
wherein the memory cell is refreshed in a centralized manner in the centralized refresh state, an internal power source circuit is partially turned OFF in the power-OFF state, and the internal power source circuit having been partially turned OFF is turned ON in the power-ON state.
In the foregoing, a preferable mode is one wherein, in the ultra-low power consumption mode, an error correcting circuit encode state and an error correcting circuit decode state are provided and wherein, in the error correcting circuit encode state, an arithmetic operation is performed on parity bits by the error correcting circuit to restore the memory cell whose maintaining (holding) characteristics are deteriorated and wherein, in the error correcting encode state, an error correction is made by the error correcting circuit based on results from the arithmetic operations.
Also, a preferable mode is one wherein the error correcting circuit operates in synchronization with a clock produced internally or fed from an external.
Also, a preferable mode is one wherein a state signal indicating that the semiconductor storage device is internally put in the ultra-low power consumption mode is output to an external.
Also, a preferable mode is one wherein the semiconductor storage device is configured to operate in a self-refresh mode such that the memory cell is periodically and automatically refreshed.
Also, a preferable mode is one wherein, in the centralized refresh state, the refresh process is performed on the memory cell in a period being shorter than that being corresponded to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein, wherein, in the power-OFF state, all power sources other than paired poles in the internal power source circuit are turned OFF.
Also, a preferable mode is one wherein, in the power-OFF state, leak paths of peripheral circuits of a memory cell array made up of a plurality of the memory cells are interrupted.
Also, a preferable mode is one wherein transition to the centralized refresh state occurs when instructions for the semiconductor storage device to be put in the ultra-low power consumption mode are provided and then transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized state are repeated.
Also, a preferable mode is one wherein, in the ultra-low power consumption mode, if the semiconductor storage device is put in the centralized refresh state when instructions for exiting the ultra-low power consumption mode are provided, transition occurs to a self-refresh state in which the memory cell is refreshed in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein, in the ultra-low power consumption mode, if the semiconductor storage device is put in the power-OFF state when instructions for exiting the ultra-low power consumption mode are provided, transition occurs to a self-refresh state in which the memory cell is refreshed in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein, when instructions for the semiconductor storage device to be put in the ultra-low power consumption mode are provided, transition to the error correcting circuit encode state and to the centralized refresh state sequentially occur and, until instructions for exiting the ultra-low power consumption mode are provided, transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized refresh state are repeated.
Also, a preferable mode is one wherein, when instructions for the semiconductor storage device to be put in the ultra-low power consumption mode are provided, transition to the error correcting encode state, to the power-OFF state, and to the centralized refresh state sequentially occurs and, until instructions for exiting the ultra-low power consumption mode are provided, transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized refresh state are repeated.
Also, a preferable mode is one wherein, in the ultra-low power consumption mode, if the semiconductor storage device is put in the centralized refresh state when the ultra-low power consumption mode exits, transition to the error correcting circuit decode state occurs and then transition occurs to a self-refresh state in which the memory cell is refreshed in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein, in the ultra-low power consumption mode, if the semiconductor storage device is put in the power-OFF state when instructions for exiting the ultra-low power consumption mode are provided, transition to the power-ON state and to the error correcting circuit decode state sequentially occurs and then transition occurs to a self-refresh state in which the memory cell is refreshed in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein, in the ultra-low power consumption mode, if the semiconductor storage device is put in the error correcting circuit encode state when instructions for exiting the ultra-low power consumption mode are provided, after termination of the error correcting circuit encode state, transition occurs to a self-refresh state in which the memory cell is refreshed in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one, wherein instructions are provided to put the semiconductor storage device into the ultra-low power consumption mode by a first change occurring in a specified signal fed from an external and to exit the ultra-low power consumption mode by a second change occurring in the specified signal.
Also, a preferable mode is one wherein, after instructions have been provided for exiting the ultra-low power consumption mode, instructions are provided for transition of an internal state of the semiconductor storage device to an idle state where no operation is performed again by the second change occurring in the specified signal.
Also, a preferable mode is one wherein, after having the specified signal produce the second change in order to give instructions for exiting the ultra-low power consumption mode, when maximum time or more required for error corrections in the error correcting circuit decode state has elapsed, the second change is produced in the specified signal used to give instructions for transition of an internal state of the semiconductor storage device to the idle state.
According to a second aspect of the present invention, there is provided a semiconductor storage device having a memory cell which must be refreshed to maintain data, including:
a self-refresh executing unit to refresh the memory cell;
an internal power source circuit to provide power to each of components; and
a controller, when instructions are provided for operations in an ultra-low power consumption mode in order to exert power control in a standby state, to have the self-refresh executing unit execute refresh operations in a centralized refresh state in which a centralized refresh process is performed on the memory cell, in a power-OFF state in which the internal power source circuit is partially turned OFF, and in a power-ON state in which the internal power source circuit having been partially turned OFF is turned ON.
In the foregoing, a preferable mode is one that where includes an error correcting circuit used to perform arithmetic operations on parity bits to restore the memory cell whose maintaining characteristics are deteriorated and to make error corrections based on results from the arithmetic operations and wherein the controller executes operations in an error correcting circuit encode state to have the error correcting circuit perform the arithmetic operations and in an error correcting circuit decode state to have the error correcting circuit make the error correction.
Also, a preferable mode is one wherein the error correcting circuit operates in synchronization with a clock occurring internally or being fed from an external.
Also, a preferable mode is one wherein the controller outputs a state signal indicating that the semiconductor storage device is internally put in the ultra-low power consumption mode.
Also, a preferable mode is one wherein a self-refresh mode is used which is able to perform the refresh operations periodically and automatically.
Also, a preferable mode is one wherein the controller has, in the centralized refresh state, the refresh executing unit perform the refresh process in a period being shorter than that corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein the controller, in the power-OFF state, turns OFF all power sources other than paired poles in the internal power source circuit.
Also, a preferable mode is one wherein the controller, in the power-OFF state, interrupts a leak path of peripheral circuits of a memory array made up of a plurality of the memory cells.
Also, a preferable mode is one wherein the controller, when instructions are provided for operations in the ultra-low power consumption mode, changes an internal state of the semiconductor storage device to the centralized refresh state and, until instructions for exiting the ultra-low power consumption mode are provided, repeats transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized refresh state.
Also, a preferable mode is one wherein the controller, in the ultra-low power consumption state, if the semiconductor storage device is put in the centralized refresh state when instructions for exiting the ultra-low power consumption state are provided, induces occurrence of transition of an internal state of the semiconductor storage device to a self-refresh state in which a refresh process is performed on the memory cell in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein the controller, in the ultra-low power consumption mode, if the semiconductor storage device is put in the power-OFF state when instructions for exiting the ultra-low power consumption mode are provided, changes an internal state of the semiconductor storage device to the power-ON state and then induces occurrence of transition to a self-refresh state in which a refresh process is performed on the memory cell in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein the controller, when instructions for operations in the ultra-low power consumption are provided, sequentially changes an internal state of the semiconductor storage device to the error correcting circuit encode state and to the centralized refresh state and, until instructions for exiting the ultra-low power consumption are provided, repeats transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized refresh state.
Also, a preferable mode is one wherein the controller, when instructions for operations in the ultra-low power consumption are provided, sequentially changes an internal state of the semiconductor storage device to the error correcting circuit encode state, to the power-OFF state, and to the centralized refresh state and, until instructions for exiting the ultra-low power consumption are provided, repeats transition from the centralized refresh state to the power-OFF state, from the power-OFF state to the power-ON state, and from the power-ON state to the centralized refresh state.
Also, a preferable mode is one wherein the controller, in the ultra-low power consumption mode, if the semiconductor storage device is put in the centralized refresh state when instructions for exiting the ultra-low power consumption mode are provided, changes an internal state of the semiconductor storage device to the error correcting circuit decode state and then induces occurrence of transition of an internal state of the semiconductor storage device to a self-refresh state in which a refresh process is performed on the memory cell in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein the controller, in the ultra-low power consumption mode, if the semiconductor storage device is put in the power-OFF state when instructions for exiting the ultra-low power consumption mode are provided, changes an internal state of the semiconductor storage device to the power-ON state and to the error correcting circuit decode state and then induces occurrence of transition of an internal state of the semiconductor storage device to a self-refresh state in which a refresh process is performed on the memory cell in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein the controller, in the ultra-low power consumption mode, if the semiconductor storage device is put in the error correcting circuit encode state when instructions for exiting the ultra-low power consumption mode are provided and after the error correcting circuit encode state has been terminated, induces occurrence of transition of an internal state of the semiconductor storage device to a self-refresh state in which a refresh process is performed on the memory cell in a period corresponding to a maintaining characteristic of the memory cell.
Also, a preferable mode is one wherein instructions for operations in the ultra-low power consumption mode are provided by a first change occurring in the specified signal and instructions for exiting the ultra-low power consumption mode are provided by a second change occurring in the specified signal.
Also, a preferable mode is one wherein, after the ultra-low power consumption mode has been exited, instructions for transition of an internal state of the semiconductor storage device into an idle state in which no operation is performed are provided by the second change again occurring in the specified signal.
Furthermore, a preferable mode is one wherein, after the second change has occurred in the specified signal which are used to provide instructions for exiting the ultra-low power consumption mode and when maximum time or more required for error correction in the error correcting circuit decode state has elapsed, the second change is produced in the specified signal to provide instructions for transfer of an internal state of the semiconductor storage device to the idle state.
With the above configurations, an ultra-low power consumption mode is employed in which power control can be exerted in a standby state. In the ultra-low power consumption mode, a centralized refresh state, power-OFF state, and power-ON state are provided. In the centralized refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, internal power source circuit can be partially turned OFF. In the power-ON state, the internal power source having been partially turned OFF is turned ON. Therefore, it is possible to greatly reduce power consumption in a standby state.